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Arsene (PO‘27) is a Computer Science and Geology Double Major and a Data Science Minor, and plays for the Claremont Colleges Mens’ Volleyball Club. His main career interest lies in Cybersecurity, and he is aiming to complete his CompTIA Security+ certification by the end of Summer 2026.
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Connor (PO’27) is a Computer Science major and Data Science minor, as well as a member of the Pomona-Pitzer football team. I am interested in programming and data analysis, and particularly how the two can be used to improve real world issues.
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Henry (PO’28) is a double major in Mathematics and Computer Science at Pomona College. Beyond the classroom, I’m a member of the varsity swim team, which has really shaped my discipline and drive. I’m naturally drawn to this research because it challenges me to apply my technical background to new areas of CS that are still being explored. Outside of Pomona, I love to play games, take photos (both film and digital), and kiteboard.
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Philippe (PO’27) is a computer science major at Pomona College. He is originally from Cameroon. He is fluent in French and English and a soccer fan. He plays pick up soccer and watches anime for fun.
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Sophie (PO ‘28) is a CS major. Her two cats, Curu and Nolo, are named after Tolkien Elves.
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Stevie (PO’26) joined the PCAL group in Spring 2026. He loves to spend his free time playing video games, watching anime/reading manga, and eating great food. He also loves to tinker with tech and built himself and his friends custom PCs and keyboards. This led him to develop an interest in understanding how computers work, which is exactly what led him to take an interest in computer architecture and subsequently joining PCAL in his last semester at Pomona. After graduating from Pomona College in 2026, he currently works as a UPenn Teaching Fellow at Princeton Day School, where he teaches computer science to middle and high school students.
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Vadym (PO’27) is originally from Kyiv, Ukraine, and currently a Computer Science student at Pomona College. I first came to the U.S. as a high school exchange student in rural Maine, and I really enjoyed the experience. I like traveling and hope to visit every country by the age of 30. While studying abroad in Melbourne last fall, I’ve also gotten into climbing, and I’m usually running on some form of caffeine (flat white is my favorite).
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Henry Cannon, Connor Wang, and Stevie Kim have all joined the PCAL group working on individual projects as RAs. Henry is working on a secure/compressed co-designed memory, Connor is working on a parallelized version of the gem5 simulator, and Stevie is working on a concurrent skip list for CXL.
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The PCAL group went to the 2026 SoCal Programming Languages and Systems Workshop to present three in progress works! Stevie gave a presentation titled “CXip List: A CXL-aware Skip List”, Henry presented a poster titled “Scr Mmy: A Co-Designed Secure and Compressed Memory”, and Connor had a poster titled “The Microservice-ization of gem5” (presented by Prof. Thomas).
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Congratulations to Steven Kim ‘26 on his graduation! Stevie is off to teach high school in Princeton, NJ. Thank you for all of your hard work and contributions to the group, Stevie!
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Arsene Laurent, Philippe Esamma (co-advised with Prof. Mik Zlatin), Sophie Park, and Vadym Musiienko have all began summer research in the PCAL group!
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The PCAL group is headed to ISCA! We are looking forward to sharing our work and hearing about the state-of-the-art. Please reach out if you would like to connect!
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Secure memory and compressed memory systems both rely on extensions to the memory controller to implement their desired properties. This project explores the co-design of the metadata fields in order to hide the latency of compression behind the authentication cost in a secure memory.
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CXL is an emerging memory system, and designing secure memory for this platform provides significant opportunitites and challenges. This project plays with the notion of the trusted computing base in a CXL system to implement secure memory optimizations.
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Given the potential heterogeneity of memory devices in a CXL system, designing systems (e.g., concurrent data structures) in an architecture-aware manner remains an open problem. This project explores system-level design decisions and proposed architectural modifications to enable efficient designs.
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It has been demonstrated that Belady’s Min algorithm is suboptimal for metadata caching. In this project (co-advised by Prof. Mik Zlatin), we prove formally the computability of this task.
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We are developing an engine that allows for events to be handled in parallel by worker threads via a dependence-aware scheduler.
Published in , 2026
Abstract. In computer architecture, gem5 represents the state-of-the-art microarchitectural simulator. It allows for running real programs end-to-end under timing-accurate full system hardware modeling with configurable components in terms of size, latency, bandwidth, and customizable logic. As such, the simulator has tens of thousands of active users in academia and industry. Unfortunately, the tool is extraordinarily arduous to use. Executing a simple “Hello world!” runs for over 300× longer on the simulated platform as it takes for the simulator to run. For more complex simulations, this implies hours of execution to simulate a few seconds of software. This work identifies a significant opportunity for improvement. At its core, gem5 is an single threaded, event-based simulator: hardware routines are encoded as lambda functions with a timestamp and placed in a central priority queue